The present invention relates to a system for protecting electrical semiconductor components and circuits utilizing them from inadvertent connection or exposure to high voltage surges and more particularly to a system for protecting MOS components from excessive levels of transient voltage.
Insulated gate field effect transistors, sometimes called IGFETs, are well known and widely used in the semiconductor art, both as discrete devices and as components of integrated circuits. Such devices usually include, in a semiconductor body such as silicon, a source region and a drain region separated from the source region by a channel region. Current flow through the channel, between source and drain, is controlled by a gate electrode physically separated from the channel by an insulative layer. The gate is capacitively coupled to the channel through the insulative layer, which serves as the capacitor dielectric, and voltage signals applied to the gate determine whether current flow through the channel is turned ON (increased) or turned OFF (diminished).
In an IGFET of, for example, silicon semiconductor material, and when the insulative material between the gate electrode and the channel in the silicon is an oxide of silicon or a material including as a significant portion an oxide of silicon, the term "MOS" (Metal-over-Oxide-over-Silicon) is often used. MOS describes the three layered structure constituted by the gate electrode of metal (or other suitable electrically conductive material such as low resistivity polycrystalline silicon) overlying the oxide insulative layer, which in turn overlies the channel. By extension, the term NMOS is conventionally used to mean an IGFET of the MOS type wherein the source and drain regions are of N-type conductivity and the channel region between source and drain is converted to N-type conductivity responsive to the gate signal so as to promote conduction through the channel between source and drain. Also, the term PMOS is conventionally applied to MOS structures wherein the source and drain regions are usually of P-type conductivity. The term CMOS, or Complimentary MOS, is conventionally applied to products wherein both NMOS and PMOS devices are cooperatively utilized.
Performance of such devices, in terms for example of desirably increased speed of response to an applied gate signal, and desirably reduced amplitude of gate signal voltage necessary to produce an intended effect on current flow through the channel, is enhanced by decreasing the thickness of the insulative layer physically separating and capacitively coupling the gate and the channel. Consequently such insulative layers are normally made quite thin, on the order of a few hundreds of angstroms in thickness.
MOS components are relatively sensitive, delicate objects, susceptible to damage due, among other things, to physical handling, thermal shock and electrical shock. Both human handling (placement, shipment and the like) as well as automatic handling equipment can be responsible for such damage, when it occurs.
In the fields of physical handling and thermal shock, absorbant packaging and insulating materials, respectively, can alleviate the problems. Electrical hazards, however, pose a different and somewhat more vexing problem.
The most dangerous and unpredictable type of static electricity damage can occur when a human comes into contact with a MOS component. In that case, a high voltage surge can be generated and can damage the component.
Unfortunately, the desirable thinness of the insulative layer of silicon oxide or other suitable insulative material in MOS components beneath the gate electrode makes this insulative layer susceptible to deleterious effects. Specifically, apertures or conductive paths therethrough can be formed, as can other forms of destruction occur, as a result of the aforementioned exposure or connection to static electric charge. Such damage renders the insulative layer permanently unsuitable for continuing service as the dielectric between gate and channel, thus effectively making the IGFET inoperative for its intended purpose.
Numerous solutions to this problem have been attempted, including surrounding and protecting components with electrically insulating materials and attempting to eliminate the voltage potential between human and component by grounding both or by some other means. Unfortunately, none of the aforementioned techniques is foolproof or even feasible for all situations. Many solutions require the redesign of MOS components themselves. In some cases, cumbersome additional components are required to filter or otherwise mitigate the harmful effects of high voltage transients. Electrical static discharge (ESD) circuits, for example, are not entirely reliable, especially for sudden, high voltage impulses, as are common with human contact. None of the prior art solutions has been totally satisfactory.
The capability of an IGFET to withstand static electric charge encountered in normal handling, without destructive effect, would be enhanced by providing supplemental static charge isolation means in association with the gate electrode. Preferably this isolation means would take the form of a transmission gate arranged in series with the normal gate of the IGFET, serving to isolate and inhibit any flow of static charge current through the insulative layer underlying the normal gate.
It would be advantageous to provide a voltage protection system in a semiconductor package to protect electronic components.
It would also be advantageous to provide a voltage protection device to protect electronic components especially from sudden voltage transients as can occur during human handling.
It would also be advantageous to provide a voltage protection system that does not require redesign of electronic components to be protected.
It would also be advantageous to provide an IGFET of improved construction having enhanced ability to withstand exposure to static electric charge encountered in normal handling.
It would also be advantageous to provide an improved IGFET of the foregoing character for use in NMOS, PMOS and CMOS applications, whose enhanced static-charge withstanding capability is secured in an economically practical fashion, and which provides improved reliability and endurance without significant sacrifice in operating efficiency and without involving undue circuit complexity.
It would also be advantageous to provide a simple system for protecting electronic components so that the manufacturing costs thereof would not be unreasonably high.
It would also be advantageous to provide a system for protecting MOS components that would require only a minimal amount of circuitry and additional components.